Pace: a Prototype Design

T.J.Reynolds, M.E.Waite and F.Z.Ieromnimon Department of Computer Science, University of Essex, Colchester CO4 3SQ, UK telephone +44 206 872680 email [reynt, waitm, ierof]@essex.ac.uk Abstract The PACE architecture exploits the potential for fine-grained parallelism in the execution of functional languages. It is an extensible, distributed memory, multiprocessor architecture that is designed specifically to support the graph reduction model of computation. PACE differs from most other research projects in this area in that it advocates the use of a specially designed processor, rather than currently available devices, as the basic replicable node. In this paper we present the design of a prototype version of the new processor, together with some results obtained by simulating the parallel execution of example programs on both a detailed Verilog description of the hardware and a much faster C-simulator.